The present invention generally relates to semiconductor device manufacturing, and more particularly to fabricating a metal line interconnect (via) fully aligned to both a Mx level and a Mx+1 level.
The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated circuits (ULSI) requires an interconnect structure including metallic wiring that connects individual devices in a semiconductor chip, to one another. Typically, the wiring interconnect network consists of two types of features that serve as electrical conductors: line features that traverse a distance across the chip, and via features which connect lines in different levels. Typically, the conducting metal lines and vias are comprised of aluminum or copper and are insulated by the interlayer dielectrics (ILD) which are electrical insulators.
In order to improve performance, the semiconductor industry has shrunk the gate length and, as a result, the chip size. As a consequence the interconnect structure that forms the metallic circuitry has also shrunk.
Traditionally, the via levels are one of the most challenging to print with a high process latitude. In order to improve the manufacturability of the lithography step, advanced masks that incorporate phase-shifting and optical proximity correction have been employed. In addition, as the size scale of these interconnects decrease, there is growing concern that overlay error between features in the interconnect structure may lead to reliability issues. Overlay errors result from misalignment during the lithography process as the mask invariably may not be perfectly aligned to the underlying structure. Although overlay errors can be minimized by reworking the lithography, some level of overlay error is unavoidable.
Two key failure modes for interconnects, that may be dependent on overlay error of lithographic patterns, are electromigration (EM) and time dependent dielectric breakdown (TDDB). This is of critical importance, as devices must be fabricated in a manner that enables their function over useful lifetimes and in various environments.
Electromigration failure results when a void forms in the conducting metal feature through metal diffusion leading to a short (or very high resistance) in the circuitry. The mechanism of electromigration is highly dependent upon the current density and the cross section of the metal features. If the wiring is constructed such that the intersection between the via and line is too small, smaller voids formed by electromigration can lead to failure which shortens the electromigration lifetime.
Time dependent dielectric breakdown (TDDB) is a failure mode whereby the insulating materials (or layers) no longer serve as adequate electrical insulators resulting in unintended conductance between two adjacent metal features. This phenomenon is highly dependent upon the electrical field between the metal features as regions with higher electrical fields are more susceptible to TDDB failure. Consequently, it is critical to control the spacing between conducting metal features in order to maintain electrical fields to tolerable levels.